dsPICDEM? MC1H 3-Phase High Voltage Power Module
1.2.4
Power-Up/Power-Down Sequence
The user should ensure that the following sequence are followed.
1.2.4.1
POWER-UP SEQUENCE
? With the development board plugged in, turn on the power supply feeding the
control PCB (if not already on).
? One or more of the fault lights may illuminate. This is normal.
? Turn on the AC supply to the power module.
? Reset the system by activating the active high ISO_RESET line. The ISO_RESET
line is on pin 33 of the 37-pin, D-type (see Section 1.7 “User Signal Connector
Pinout (37-Pin, D-Type)” ). If using the dsPICDEM MC1 Motor Control
Development Board, this signal is routed to pin 14 of the 30F6010 dsPIC device,
which is on Port RE9. The minimum pulse width for the RESET is 2 μ s. The
RESET should be done in coordination with the SPI? handling routine of the
dsPIC device to ensure correct synchronization of the serial interface providing
the isolated voltage feedback (see Section 1.2.6.2 “Isolated Feedback” and
Section 1.4.7.2 “Isolated Voltage Feedback” ). The system is now ready to use.
1.2.4.2
POWER-DOWN SEQUENCE
? Stop firing all power devices.
? Turn off the incoming AC supply.
? Wait until the red DC bus LED indicator visible through the ventilation holes in the
top of the unit has gone out (this will take 3 minutes or less).
? Turn off the power supply feeding the control card (if required).
1.2.5
Power Device Switching Frequencies
The PFC stage has been designed for a switching frequency of 50 kHz (±5%).
This offers a good system compromise between cost, size and efficiency. The
modulation frequency affects not only the losses in the power switches and diode but
also that in the PFC inductor and snubbing components. The user should not deviate
from the stated carrier frequency. The user should note that a typical regulation level
for the DC bus is between 350-400V.
If the user does not wish to use the PFC stage the PFC switches can simply be
left off. However, the PFC inductor and diode will be left in circuit and the input
current will remain limited to 5A (RMS) and 8.9A Peak. The user should read Section
1.5.3.3 “Bypassing The PFC” if this is unacceptable.
The Brake chopper switch has been designed so that it may be switched up to a
maximum frequency of 16 kHz. This frequency limit is chosen for power dissipation
and low voltage power supply consumption reasons. In most braking applications a
lower modulation frequency will be used, as there is little benefit (apart from acoustic
noise) from modulating at such a high frequency.
The six inverter switches have been designed so that they may be switched up
to a maximum frequency of 20 kHz. This frequency limit is chosen for power
dissipation and low voltage power supply consumption reasons. Unless extremely low
output current harmonics or very high bandwidth control is required, it is suggested
that a 16 kHz carrier frequency be used. This offers lower loss while still being
inaudible. It also has the advantage that the dead time insertion will cause less
distortion of the output voltage.
DS70096A-page 10
? 2003 Microchip Technology Inc.
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